Low noise amplifiers (LNAs) are extensively used in radio frequency (RF) circuitry such as RF front end circuitry. FIG. 1 shows a conventional LNA 10. The conventional LNA 10 includes a main transistor 12, a cascode transistor 14, and biasing circuitry 16. The main transistor 12 includes a gate contact G coupled to both the biasing circuitry 16 and an input node 18, a source contact S coupled to ground via an isolation inductor L_IS, and a drain contact D. The cascode transistor 14 includes a gate contact G coupled to the biasing circuitry 16, a drain contact D coupled to both a supply voltage VCC via an isolation inductor L_IS and an output node 20, and a source contact S coupled to the drain contact D of the main transistor 12.
In operation, the biasing circuitry 16 provides biasing signals to the gate contact G of the main transistor 12 and the cascode transistor 14. Generally, the biasing signals are provided such that a majority of the supply voltage VCC is distributed across the main transistor 12. Signals provided at the input node 18 are amplified by the main transistor 12 and the cascode transistor 14 by modulating the supply voltage VCC, and are provided at the output node 20. Due to the biasing of the main transistor 12 and the cascode transistor 14 discussed above, the main transistor 12 performs the transconductance amplification, while the cascode transistor 14 performs the transresistance amplification.
In the conventional LNA 10, the main transistor 12 and the cascode transistor 14 are silicon on insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs). SOI MOSFETs are available in floating-body and body-contacted configurations. FIGS. 2A through 2C show an exemplary floating-body SOI MOSFET 22. Specifically, FIG. 2A shows a top view of the floating-body SOI MOSFET 22, FIG. 2B shows a first cross-sectional view of the floating-body SOI MOSFET 22 taken through A-A1 of FIG. 2A, and FIG. 2C shows a second cross-sectional view of the floating-body SOI MOSFET 22 taken through B-B1 of FIG. 2A. The floating-body SOI MOSFET 22 includes a substrate 24, a buried oxide layer 26 on the substrate 24, and a device layer 28 on the buried oxide layer 26. The device layer 28 includes a number of shallow trench isolation (STI) regions 30, which surround a source region 32, a body region 34, and a drain region 36. The source region 32 and the drain region 36 are separated by the body region 34. A gate oxide layer 38 is on the body region 34 and a portion of the source region 32 and the drain region 36. A gate contact 40 is on the gate oxide layer 38. A source contact 42 is on the source region 32, and a drain contact 44 is on the drain region 36.
FIGS. 3A through 3C show a body-contacted SOI MOSFET 46. Specifically, FIG. 3A shows a top view of the body-contacted SOI MOSFET 46, FIG. 3B shows a first cross-sectional view of the body-contacted SOI MOSFET 46 taken through A-A1 of FIG. 3A, and FIG. 3C shows a second cross-sectional view of the body-contacted SOI MOSFET 46 taken through B-B1 of FIG. 3A. The body-contacted SOI MOSFET 46 includes a substrate 48, a buried oxide layer 50 on the substrate 48, and a device layer 52 on the buried oxide layer 50. The device layer 52 includes a number of STI regions 54, which surround a source region 56, a body region 58, and a drain region 60. The source region 56 and the drain region 60 are separated by the body region 58. A gate oxide layer 62 is on the body region 58 and a portion of the source region 56 and the drain region 60. A gate contact 64 is on the gate oxide layer 62. A source contact 66 is on the source region 56 and a drain contact 68 is on the drain region 60. As shown in the top view of the body-contacted SOI MOSFET 46 shown in FIG. 3A, the gate oxide layer 62 and the gate contact 64 are formed in an “H” shape. Further, the body region 58 is extended above a top portion and a bottom portion (i.e., the outer sides of the “H” shape) of the gate oxide layer 62 and the gate contact 64. The “H” shape of the gate oxide layer 62 and the gate contact 64 separates this additional body region 58 from the source region 56 and the drain region 60 and terminates any parasitic channel effects that may occur at the edge of the additional body region 58. Essentially, the “H” shape of the gate oxide layer 62 and the gate contact 64 acts as a mask to form the various regions of the body-contacted SOI MOSFET 46. A “T” shape, an “L” shape, and a “U” shape may also be used for the gate oxide layer 62 and the gate contact 64, as required by the particular layout of the body region 58. While not shown, a silicide layer may connect the source region 56 and the body region 58 such that the body-contacted SOI MOSFET 46 is a source-to-body connected SOI MOSFET. This may require a break in the gate oxide layer 62 and the gate contact 64 (not shown).
Generally, floating-body SOI MOSFETs have higher transconductance than their body-contacted counterparts. Further, the footprint of body-contacted SOI MOSFETs is often larger than floating-body SOI MOSFETs due to the extra area required for the extended body region. This generally brings extra parasitic capacitance and thus a lower transition frequency (ft). Accordingly, floating-body SOI MOSFETs are generally the preferred configuration for SOI MOSFETs used in LNAs.
While floating-body SOI MOSFETs are generally preferred over body-contacted SOI MOSFETs for LNAs, these devices exhibit a marked increase in noise when operated at high drain-to-source voltages. Further, fluctuations in the supply voltage provided to floating-body SOI MOSFETs may result in significant increases in noise. This is due to the well-known phenomena of charge storage within the floating-body region, which changes the threshold voltage of the device and causes a “kink” in the current vs. voltage response thereof. FIG. 4 illustrates a drain current density vs. drain-to-source voltage response of a floating-body SOI MOSFET for both a partial depletion and a total depletion device (the partial depletion device is shown as a dashed line 70 and the total depletion device is shown as a solid line 72). As shown in FIG. 4, the current density in each device remains relatively constant to a particular voltage, after which a “kink” in the response is presented. This “kink” results in significant distortion due to a non-linear response of the device. To avoid such effects, the biasing circuitry 16 discussed above generally attempts to bias the main transistor 12 at a voltage below the “kink” and the cascode transistor 14 at a voltage above the “kink”. However, changing supply voltages due to different battery conditions in a mobile device may make it impossible to avoid these “kinks” and thus result in significant distortion in the conventional LNA 10. Specifically, as the supply voltage is reduced due to battery discharge, it may cause one of the main transistor 12 and the cascode transistor 14 to reach the “kink” and therefore exhibit a non-linear response.
Body-contacted SOI MOSFET devices do not suffer from the aforementioned noise problems and do not experience the “kink” effect as described above. This is illustrated in FIG. 4 by a long-dashed line 74. As shown in FIG. 4, the current density vs. voltage response of a body-connected device remains relatively linear over most of the voltage range. This is due to the fact that charge carriers may be removed from the body as necessary via the contacted body, thereby avoiding a change in threshold voltage as charge carriers accumulate in the body. However, using body-contacted SOI MOSFET devices in place of the floating-body SOI MOSFET devices generally results in similarly poor performance due to the relatively low transconductance and higher junction capacitance of these devices. Accordingly, there is a need for an LNA with improved performance at high frequencies.